ADS6444IRGCT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADS6444IRGCT

QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

STMicroelectronics 

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531 – MAY 2007

VCC

Reference Clock

REF_IN

Y0

VCC

Y0B

CDCM7005

VCXO

OUTP

OUTM

VCXO_INP

VCXO_INM

CTRL

CLKP

CLKM

ADS6xxx

www.ti.com

S0238-02

Figure 91. PECL Clock Drive Using CDCM7005

Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a

0.1-µF capacitor, as shown in Figure 92.

CMOS Clock Input

0.1 mF

CLKP

0.1 mF

CLKM

ADS6xxx

S0168-07

Figure 92. Single-Ended Clock Driving Circuit

For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode

noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass

filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a

non-50% duty cycle clock input.

CLOCK BUFFER GAIN

When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is

increased. Hence, it is recommended to use large clock amplitude. As shown by Figure 18, use clock amplitude

greater than 1VPP to avoid performance degradation.

In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock

amplitude. The gain can be set by programming the register bits <CLKIN GAIN> (refer to Table 14) and

increases monotonically from Gain 0 to Gain 4 settings. Table 22 lists the minimum clock amplitude supported

for each gain setting.

54

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