ADSP-BF516KSWZ-3(RevD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF516KSWZ-3
(Rev.:RevD)

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16

SDRAM Interface Timing

Table 28. SDRAM Interface Timing

VDDMEM

1.8V Nominal

VDDMEM

2.5 V/3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

tSSDAT

Data Setup Before CLKOUT

tHSDAT

Data Hold After CLKOUT

Switching Characteristics

1.5

1.5

ns

1.3

0.8

ns

tSCLK

tSCLKH

tSCLKL

tDCAD

tHCAD

tDSDAT

tENSDAT

CLKOUT Period1

CLKOUT Width High

CLKOUT Width Low

Command, Address, Data Delay After CLKOUT2

Command, Address, Data Hold After CLKOUT2

Data Disable After CLKOUT

Data Enable After CLKOUT

12.5

10

ns

5

4

ns

5

4

ns

5

4

ns

1

1

ns

5.5

5

ns

0

0

ns

1 The tSCLK value is the inverse of the fSCLK specification discussed in Table 12 on Page 23. Package type and reduced supply voltages affect the best-case value listed here.

2 Command pins/balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

CLKOUT

DATA (IN)

DATA (OUT)

COMMAND,

ADDRESS

(OUT)

tSSDAT

tSCLK

tHSDAT

tENSDAT

tSCLKL

tSCLKH

tDCAD

tHCAD

tDSDAT

tDCAD

tHCAD

NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Figure 13. SDRAM Interface Timing

Rev. D | Page 33 of 68 | April 2014

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