ADSP-BF516KSWZ-3(RevD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF516KSWZ-3
(Rev.:RevD)

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16

Table 8. Signal Descriptions (Continued)

Signal Name

Type Function

Driver

Type1

Port J

PJ0:SCL

I/O 5V TWI Serial Clock (This signal is an open-drain output and requires a pull-up E

resistor. Consult version 2.1 of the I2C specification for the proper resistor value.)

PJ1:SDA

I/O 5V TWI Serial Data (This signal is an open-drain output and requires a pull-up E

resistor. Consult version 2.1 of the I2C specification for the proper resistor value.)

Real Time Clock

RTXI

I

RTC Crystal Input (This ball should be pulled low when not used.)

RTXO

O RTC Crystal Output (Does not three-state during hibernate)

JTAG Port

TCK

I

JTAG Clock

TDO

O JTAG Serial Data Out

C

TDI

I

JTAG Serial Data In

TMS

I

JTAG Mode Select

TRST

I JTAG Reset (This signal should be pulled low if the JTAG port is not used.)

EMU

O Emulation Output

C

Clock

CLKIN

I

Clock/Crystal Input

XTAL

O Crystal Output (If CLKBUF is enabled, does not three-state during hibernate)

CLKBUF

O Buffered XTAL Output (If enabled, does not three-state during hibernate)

C

Mode Controls

RESET

I

Reset

NMI

I

Non-maskable Interrupt (This signal should be pulled high when not used.)

BMODE2-0

I

Boot Mode Strap 2-0

Voltage Regulation Interface

PG

I

Power Good (This signal should be pulled low when not used.)

EXT_WAKE

O Wake up Indication (Does not three-state during hibernate)

C

Power Supplies

ALL SUPPLIES MUST BE POWERED See Operating Conditions on Page 22.

VDDEXT

VDDINT

VDDRTC

VDDFLASH

VDDMEM

VPPOTP

VDDOTP

GND

P I/O Power Supply

P Internal Power Supply

P Real Time Clock Power Supply

P Internal SPI Flash Power Supply

P MEM Power Supply

P OTP Programming Voltage

P OTP Power Supply

G Ground for All Supplies

1 See Output Drive Currents on Page 52 for more information about each driver type.

2 When driven low, the PF15 signal can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as PHYINT. If the pin/ball

is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the signal with a resistor.

3 Boot host wait is a GPIO signal toggled by the boot kernel. The mandatory external pull-up/pull-down resistor defines the signal polarity.

4 A pull-up resistor is required for the boot from external SPI EEPROM or flash (BMODE = 0x3).

Rev. D | Page 21 of 68 | April 2014

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