ADSP-BF516KSWZ-3(RevD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF516KSWZ-3
(Rev.:RevD)

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16

TIMING SPECIFICATIONS

Clock and Reset Timing

Table 24 and Figure 9 describe clock and reset operations. Per

the CCLK and SCLK timing specifications in Table 10, Table 11,

and Table 12 on Page 23, combinations of CLKIN and clock

multipliers must not select core/peripheral clocks in excess of

the processor’s speed grade.

Table 24. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

fCKIN

CLKIN Frequency (Commercial/Industrial Models1, 2, 3, 4 12

50

fCKIN

CLKIN Frequency (Automotive Models)1, 2, 3, 4

14

50

tCKINL

CLKIN Low Pulse1

10

tCKINH

CLKIN High Pulse1

10

tWRST

RESET Asserted Pulse Width Low5

11 × tCKIN

Switching Characteristic

MHz

MHz

ns

ns

ns

tBUFDLAY

CLKIN to CLKBUF Delay

11

ns

1 Applies to PLL bypass mode and PLL nonbypass mode.

2 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 10 through Table 12 on Page 23.

3 The tCKIN period (see Figure 9) equals 1/fCKIN.

4 If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.

5 Applies after power-up sequence is complete. See Table 25 and Figure 10 for power-up reset timing.

CLKIN

CLKBUF

tCKIN

tCKINL

tCKINH

RESET

tWRST

tBUFDLAY

tBUFDLAY

Figure 9. Clock and Reset Timing

Rev. D | Page 29 of 68 | April 2014

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