ADSP-BF516KSWZ-3(RevD) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF516KSWZ-3 Datasheet PDF : 68 Pages
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ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Parameter
Test Conditions
Min
Typical Max
IDDFLASH1
Flash Memory Supply Current 1
—Asynchronous Read
6
9
IDDFLASH2
Flash Memory Supply Current 2
—Standby
15
25
IDDFLASH3
Flash Memory Supply Current 3
—Program and Erase
20
25
IDDOTP
VDDOTP Current
VDDOTP = 2.5 V, TJ = 25°C,
2
OTP Memory Read
IDDOTP
VDDOTP Current
VDDOTP = 2.5 V, TJ = 25°C,
2
OTP Memory Write
IPPOTP
VPPOTP Current
VPPOTP = 2.5 V, TJ = 25°C,
100
OTP Memory Read
IPPOTP
VPPOTP Current
VPPOTP = Table 20 V, TJ = 25°C,
3
OTP Memory Write
1 Applies to input balls.
2 Applies to JTAG input balls (TCK, TDI, TMS, TRST).
3 Applies to three-statable balls.
4 Applies to bidirectional balls SCL and SDA.
5 Applies to all signal balls, except SCL and SDA.
6 Guaranteed, but not tested.
7 See the ADSP-BF51x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
8 Includes current on VDDEXT, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low.
9 Guaranteed maximum specifications.
10Unit for VDDINT is V (Volts). Unit for fSCLK is MHz.
11See Table 13 for the list of IDDINT power vectors covered.
Unit
mA
μA
mA
mA
mA
μA
mA
Total Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 24 shows the
current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP
specifies static power dissipation as a function of voltage
(VDDINT) and temperature (see Table 14), and IDDINT specifies the
total power specification for the listed test conditions, including
the dynamic component as a function of voltage (VDDINT) and
frequency (Table 15).
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core and
L1 memories (Table 13).
The ASF is combined with the CCLK Frequency and VDDINT
dependent data in Table 15 to calculate this part. The second
part is due to transistor switching in the system clock (SCLK)
domain, which is included in the IDDINT specification equation.
Table 13. Activity Scaling Factors (ASF)1
IDDINT Power Vector
Activity Scaling Factor (ASF)
IDD-PEAK
1.29
IDD-HIGH
1.25
IDD-TYP
1.00
IDD-APP
0.85
IDD-NOP
0.70
IDD-IDLE
0.41
1 See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
(EE-297). The power vector information also applies to the ADSP-BF51x
processors.
Table 14. Static Current—IDD-DEEPSLEEP (mA)
TJ (°C)1
–40
–20
0
1.10 V
0.9
1.0
1.2
1.15 V
1.0
1.1
1.3
1.20 V
1.0
1.2
1.4
1.25 V
1.1
1.3
1.6
Voltage (VDDINT)1
1.30 V
1.35 V
1.1
1.2
1.4
1.6
1.8
2.0
1.40 V
1.3
1.7
2.2
1.45 V
1.7
1.9
2.3
1.50 V
1.9
2.0
2.5
Rev. D | Page 25 of 68 | April 2014
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