ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Table 25. Power-Up Reset Timing
Parameter
Timing Requirements
tRST_IN_PWR RESET Deasserted after the VDDINT, VDDEXT, VDDRTC, VDDMEM, VDDOTP, and CLKIN Pins are
Stable and Within Specification
Min
3500 × tCKIN
Max
Unit
ns
RESET
tRST_IN_PWR
CLKIN
VDD_SUPPLIES
Figure 10. Power-Up Reset Timing
Rev. D | Page 30 of 68 | April 2014