ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
RSCLKx
SAMPLE EDGE
tHOFSI
RFSx
(OUTPUT)
tDFSI
RFSx
(INPUT)
tSFSI
tHFSI
DRx
tSDRI
tHDRI
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
TSCLKx
SAMPLE EDGE
tHOFSI
TFSx
(OUTPUT)
tD FSI
TFSx
(INPUT)
tHDTI
DTx
tDDTI
tSFSI
tHFSI
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
tSCLKEW
tSCLKE
RSCLKx
tHOFSE
RFSx
(OUTPUT)
tDFSE
RFSx
(INPUT)
tSFSE
tHFSE
DRx
tSDRE
tHDRE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
tSCLKE
t SCLKEW
TSCLKx
tHOFSE
TFSx
(OUTPUT)
tDFSE
TFSx
(INPUT)
tHDTE
DTx
tDDTE
tSFSE
tHFSE
Figure 22. Serial Ports
TSCLKx
(INPUT)
TFSx
(INPUT)
tSUDTE
RSCLKx
(INPUT)
RFSx
(INPUT)
tSUDRE
FIRST
Figure 23. Serial Port Start Up with External Clock and Frame Sync
Rev. D | Page 40 of 68 | April 2014