CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.9 Switching Characteristics — Internal Clock
Parameter
Symbol
Min
Max
Unit
Internal DCLK frequency1
Fdclk
-
CS49530x-CVZ
Fxtal
CS49531x-CQZ
Fxtal
CS49531x-CVZ
Fxtal
CS49530x-DVZ
Fxtal
CS49531x-DQZ
Fxtal
CS49531x-DVZ
Fxtal
150
150
150
TBD
TBD
TBD
MHz
Internal DCLK period1
DCLKP
-
ns
CS49530x-CVZ
6.7
1/Fxtal
CS49531x-CQZ
6.7
1/Fxtal
CS49531x-CVZ
6.7
1/Fxtal
CS49530x-DVZ
TBD
1/Fxtal
CS49531x-DQZ
CS49531x-DVZ
TBD
TBD
1/Fxtal
1/Fxtal
1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains
PRELIMINARY locked until the next power-on reset.
DS705PP3
Copyright 2008 Cirrus Logic
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