CS495303(2008) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS495303 Datasheet PDF : 34 Pages
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.14 Switching Characteristics — Parallel Control Port - Intel® Slave Mode
Parameter
Symbol Min
Typical
Max Unit
Address setup before PCP_CS# and PCP_RD# low or PCP_CS#
and PCP_WR# low
tias
5
-
ns
Address hold time after PCP_CS# and PCP_RD# low or PCP_CS#
tiah
5
and PCP_WR# high
-
ns
Read
Delay between PCP_RD# then PCP_CS# low or PCP_CS# then
PCP_RD# low
ticdr
0
-
ns
Data valid after PCP_CS# and PCP_RD# low
tidd
-
18 ns
PCP_CS# and PCP_RD# low for read
tirpw
24
-
ns
Data hold time after PCP_CS# or PCP_RD# high
tidhr
8
-
ns
Data high-Z after PCP_CS# or PCP_RD# high
PCP_CS# or PCP_RD# high to PCP_CS# and PCP_RD# low for
next read1
tidis
-
tird
30
18 ns
-
ns
PCP_CS# or PCP_RD# high to PCP_CS# and PCP_WR# low for
next write1
tirdtw
30
-
ns
Y PCP_RD# rising to PCP_IRQ# rising
Write
tirdirqhl
-
12 ns
Delay between PCP_WR# then PCP_CS# low or PCP_CS# then
R PCP_WR# low
ticdw
0
-
ns
Data setup before PCP_CS# or PCP_WR# high
PCP_CS# and PCP_WR# low for write
A Data hold after PCP_CS# or PCP_WR# high
PCP_CS# or PCP_WR# high to PCP_CS# and PCP_RD# low for
next read1
tidsu
8
tiwpw
24
tidhw
8
tiwtrd
30
-
ns
-
ns
-
ns
-
ns
IN PCP_CS# or PCP_WR# high to PCP_CS# and PCP_WR# low for
next write1
tiwd
30
-
ns
PCP_WR# rising to PCP_BSY# falling
tiwrbsyl
-
2*DCLKP + 20
-
ns
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by
IM the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent
overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware
PREL speed limitations.
18
Copyright 2008 Cirrus Logic
DS705PP3
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