CS495303(2008) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS495303 Datasheet PDF : 34 Pages
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.15 Switching Characteristics — Parallel Control Port - Motorola® Slave Mode
Parameter
Symbol Min
Max Unit
Address setup before PCP_CS# and PCP_DS# low
Address hold time after PCP_CS# and PCP_DS# low
Read
tmas
5
tmah
5
-
ns
-
ns
Delay between PCP_DS# then PCP_CS# low or PCP_CS# then
tmcdr
0
PCP_DS# low
-
ns
Data valid after PCP_CS# and PCP_DS# low with PCP_R/W# high tmdd
-
19
ns
PCP_CS# and PCP_DS# low for read
tmrpw
24
-
ns
Data hold time after PCP_CS# or PCP_DS# high after read
tmdhr
8
-
ns
Data high-Z after PCP_CS# or PCP_DS# high after read
tmdis
-
18
ns
PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for
tmrd
30
next read1
-
ns
PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for tmrdtw
30
next write1
-
ns
PCP_RW# rising to PCP_IRQ# falling
Y Write
tmrwirqh
-
12
ns
Delay between PCP_DS# then PCP_CS# low or PCP_CS# then tmcdw
0
PCP_DS# low
-
ns
R Data setup before PCP_CS# or PCP_DS# high
tmdsu
8
PCP_CS# and PCP_DS# low for write
tmwpw
24
A PCP_R/W# setup before PCP_CS# AND PCP_DS# low
tmrwsu
24
PCP_R/W# hold time after PCP_CS# or PCP_DS# high
tmrwhld
8
Data hold after PCP_CS# or PCP_DS# high
tmdhw
8
IN PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low with tmwtrd
30
PCP_R/W# high for next read1
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for
tmwd
30
next write1
-
ns
PCP_RW# rising to PCP_BSY# falling
tmrwbsyl
-
2*DCLKP + 20
-
ns
IM 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by
the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent
overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware
PREL speed limitations.
20
Copyright 2008 Cirrus Logic
DS705PP3
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