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CS495303(2008) View Datasheet(PDF) - Cirrus Logic

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Description
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CS495303 Datasheet PDF : 34 Pages
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode.
Parameter
Symbol Min
Typical
Max
Units
SCP_CLK frequency1
fspisck
-
25
MHz
SCP_CS# falling to SCP_CLK rising
tspicss
24
-
ns
SCP_CLK low time
tspickl
20
-
ns
SCP_CLK high time
tspickh
20
-
ns
Setup time SCP_MOSI input
tspidsu
5
-
ns
Hold time SCP_MOSI input
tspidh
5
-
ns
SCP_CLK low to SCP_MISO output valid
tspidov
-
11
ns
SCP_CLK falling to SCP_IRQ# rising
tspiirqh
-
20
ns
SCP_CS# rising to SCP_IRQ# falling
tspiirql
0
ns
SCP_CLK low to SCP_CS# rising
tspicsh
24
-
ns
SCP_CS# rising to SCP_MISO output high-Z
tspicsdz
-
20
ns
SCP_CLK rising to SCP_BSY# falling
tspicbsyl
-
3*DCLKP+20
ns
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application. Flow control using
the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed
Y is Fxtal/3.
R SCP_CS#
A SCP_CLK
IN SCP_MOSI
IM SCP_MISO
EL SCP_IRQ#
PR SCP_BSY#
tspicss
tspickl
0
1
2
6
7
0
5
6
7
tspicsh
fspisck
tspickh
A6
tspidsu
A5
tspidh
A0 R/W MSB
tspidov
MSB
LSB
tspiirqh
LSB
tspicsdz
tspiirql
tspibsyl
Figure 3. Serial Control Port - SPI Slave Mode Timing
14
Copyright 2008 Cirrus Logic
DS705PP3

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