QL5732-33BPS484M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
Manufacturer
QL5732-33BPS484M
QuickLogic Corporation
QL5732-33BPS484M Datasheet PDF : 41 Pages
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QL5732 Enhanced QuickPCI Device Data Sheet Rev. E
Twelve 8-bit MAC functions can be implemented per cycle for a total of ~1.2 billion MACs/s
when clocked at 98 MHz. Additional multiply-accumulate functions can be implemented in the
programmable logic.
The modes for the ECU block are dynamically re-programmable through the programmable logic.
Table 4: ECU Mode Select Criteria
Instruction
S1 S2 S3
Operation
ECU Performancea, -B WCC
tPD
tSU
tCO
00 0
Multiply
7.0 ns max
00 1
Multiply-Add
9.4
ns max
01 0
Accumulateb
4.1 ns 1.2 ns
min
max
01 1
Add
3.3
max
10 0
Multiply (registered)c
10.2 ns 1.2 ns
min
max
1 0 1 Multiply- Add (registered)
10.2 ns 1.2 ns
min
max
1 1 0 Multiply - Accumulate
10.2 ns 1.2 ns
min
max
11 1
Add (registered)
4.1 ns 1.2 ns
min
max
a. tPD, tSU and tCO do not include routing paths in/out of the ECU block.
b. Internal feedback path in ECU restricts max clk frequency to 224 MHz.
c. B [15:0] set to zero.
NOTE: Timing numbers in Table 1 represent -B Worst Case
Commercial conditions.
Phase Locked Loop (PLL) Information
Instead of requiring extra components, designers simply need to instantiate one of the
pre-configured models (described in this section). The QuickLogic built-in PLLs support a wider
range of frequencies than many other PLLs. These PLLs also have the ability to be cascaded to
support different ranges of frequency multiplications or divisions, driving the device at a faster or
slower rate than the incoming clock frequency. Most importantly, they achieve a very short clock-
to-out time—generally less than 3 ns. This low clock-to-out time is achieved by the PLL
subtracting the clock tree delay through the feedback path, effectively making the clock tree delay
zero.
Figure 6 illustrates a typical QuickLogic ESP PLL.
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© 2003 QuickLogic Corporation
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