QL5732-33BPS484M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
Manufacturer
QL5732-33BPS484M
QuickLogic Corporation
QL5732-33BPS484M Datasheet PDF : 41 Pages
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QL5732 Enhanced QuickPCI Device Data Sheet Rev. E
Joint Test Access Group (JTAG) Support
TCK
TMS
TRSTB
TAp Controller
State Machine
(16 States)
Instruction Decode
&
Control Logic
RDI
Mux
Instruction Register
Boundary-Scan Register
(Data Register)
Mux
TDO
Bypass
Register
Internal
Register
I/O Registers
User Defined Data Register
Figure 7: JTAG Block Diagram
JTAG pins support the IEEE Standard 1149.1a to provide boundary scan capability for the
QL5732 device. Six pins are dedicated to JTAG and programming functions on each QL5732
device; these pins are unavailable for general design input and output signals. TDI, TDO, TCK,
TMS, and TRSTB are JTAG pins. The sixth pin, STM, is used only for programming.
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design
challenges, on problem being the accessibility of test points. JTAG was formed in response to this
challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan
Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the
boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP)
controller works in concert with the Instruction Register (IR); these allow users to run three
required tests, along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse
subsystem tests for fuller verification of higher level system elements.
The JTAG 1149.1 standard requires the following three tests:
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