QL5732-33BPS484M View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL5732-33BPS484M

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5732 Enhanced QuickPCI Device Data Sheet Rev. E

AC Characteristics

The AC characteristics are calculated at 2.5 V, TA = 25°C (K = 0.74). To calculate delays, multiply

the appropriate K factor in Table 8 by the numbers presented in Table 11 through Table 17.

Table 11: Logic Cells

Symbol

Logic Cells

Parameter

Value

Min Max

tPD

Combinatorial Delay of the Longest Path: time taken by the combinatorial

circuit to output

- 0.257 ns

tSU

Setup Time: time the synchronous input of the flip flop must be stable before the

active clock edge

0.22 ns

-

tHL

Hold Time: time the synchronous input of the flip flop must be stable after the

active clock edge

0

-

tCO

Clock to Out Delay: the amount of time taken by the flip flop to output after the

active clock edge.

-

0.255 ns

tCWHI

tCWLO

tSET

Clock High Time: required minimum time the clock stays high

0.46 ns -

Clock Low Time: required minimum time that the clock stays low

0.46 ns -

Set Delay: time between when the flip flop is ”set” (high) and when the output is

consequently “set” (high)

-

0.18 ns

tRESET

Reset Delay: time between when the flip flop is ”reset” (low) and when the output

is consequently “reset” (low)

-

0.09 ns

tSW

Set Width: time that the SET signal remains high/low

tRW

Reset Width: time that the RESET signal remains high/low

0.3 ns

-

0.3 ns

-

SET

D

CLK

RESET

Q

Figure 9: Logic Cell

© 2003 QuickLogic Corporation

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