DSPIC30F1013AT-30E/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC30F1013AT-30E/ML

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC30F3014/4013

EXAMPLE 6-5: DATA EEPROM BLOCK WRITE

MOV

MOV

MOV

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

TBLWTL

MOV

MOV

DISI #5

MOV

MOV

MOV

MOV

BSET

NOP

NOP

#LOW_ADDR_WORD,W0 ; Init pointer

#HIGH_ADDR_WORD,W1

W1,TBLPAG

#data1,W2

; Get 1st data

W2,[ W0]++

#data2,W2

; write data

; Get 2nd data

W2,[ W0]++

#data3,W2

; write data

; Get 3rd data

W2,[ W0]++

#data4,W2

; write data

; Get 4th data

W2,[ W0]++

#data5,W2

; write data

; Get 5th data

W2,[ W0]++

#data6,W2

; write data

; Get 6th data

W2,[ W0]++

#data7,W2

; write data

; Get 7th data

W2,[ W0]++

#data8,W2

; write data

; Get 8th data

W2,[ W0]++

#data9,W2

; write data

; Get 9th data

W2,[ W0]++

#data10,W2

; write data

; Get 10th data

W2,[ W0]++

#data11,W2

; write data

; Get 11th data

W2,[ W0]++

#data12,W2

; write data

; Get 12th data

W2,[ W0]++

#data13,W2

; write data

; Get 13th data

W2,[ W0]++

#data14,W2

; write data

; Get 14th data

W2,[ W0]++

#data15,W2

; write data

; Get 15th data

W2,[ W0]++

#data16,W2

; write data

; Get 16th data

W2,[ W0]++

#0x400A,W0

; write data. The NVMADR captures last table access address.

; Select data EEPROM for multi word op

W0,NVMCON

; Operate Key to allow program operation

; Block all interrupts with priority <7 for

; next 5 instructions

#0x55,W0

W0,NVMKEY

#0xAA,W1

; Write the 0x55 key

W1,NVMKEY

NVMCON,#WR

; Write the 0xAA key

; Start write cycle

6.4 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

6.5 Protection Against Spurious Write

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared;

also, the Power-up Timer prevents EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch or software malfunction.

DS70138E-page 50

© 2007 Microchip Technology Inc.

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