DSPIC30F1013AT-30E/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC30F1013AT-30E/ML

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC30F3014/4013

7.0 I/O PORTS

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and

the parallel I/O ports.

All I/O input ports feature Schmitt Trigger inputs for

improved noise immunity.

7.1 Parallel I/O (PIO) Ports

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

can be read, but the output driver for the parallel port bit

is disabled. If a peripheral is enabled but the peripheral

is not actively driving a pin, that pin can be driven by a

port.

All port pins have three registers directly associated

with the operation of the port pin. The Data Direction

register (TRISx) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset.

Reads from the latch (LATx), read the latch. Writes to

the latch, write the latch (LATx). Reads from the port

(PORTx), read the port pins and writes to the port pins,

write the latch (LATx).

Any bit and its associated data and control registers

that are not valid for a particular device are disabled,

which means the corresponding LATx and TRISx

registers and the port pin read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs. An example is the

INT4 pin.

A parallel I/O (PIO) port that shares a pin with a periph-

eral is, in general, subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pad cell. Figure 7-2 shows how ports are shared

with other peripherals and the associated I/O cell (pad)

to which they are connected. Table 7-1 shows the

formats of the registers for the shared ports, PORTB

through PORTF.

Note: The actual bits in use vary between

devices.

FIGURE 7-1:

BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE

Dedicated Port Module

Read TRIS

Data Bus

WR TRIS

WR LAT +

WR Port

TRIS Latch

DQ

CK

Data Latch

DQ

CK

I/O Cell

I/O Pad

Read LAT

Read Port

© 2007 Microchip Technology Inc.

DS70138E-page 51

Share Link: