DSPIC30F1013AT-30E/ML View Datasheet(PDF) - Microchip Technology
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Description
Manufacturer
DSPIC30F1013AT-30E/ML Datasheet PDF : 220 Pages
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dsPIC30F3014/4013
FIGURE 7-2:
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Output Multiplexers
I/O Cell
1 Output Enable
0
PIO Module
Read TRIS
Data Bus
WR TRIS
WR LAT +
WR Port
DQ
CK
TRIS Latch
DQ
CK
Data Latch
1 Output Data
0
I/O Pad
Read LAT
Read Port
Input Data
7.2 Configuring Analog Port Pins
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) is
converted.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
7.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
EXAMPLE 7-1:
PORT WRITE/READ
EXAMPLE
MOV
MOV
NOP
btss
0xFF00, W0
W0, TRISB
PORTB, #11
; Configure PORTB<15:8>
; as inputs
; and PORTB<7:0> as outputs
; additional instruction
cylcle
; bit test RB11 and skip if
set
DS70138E-page 52
© 2007 Microchip Technology Inc.
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