DSPIC30F1013AT-30E/ML View Datasheet(PDF) - Microchip Technology
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DSPIC30F1013AT-30E/ML Datasheet PDF : 220 Pages
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TABLE 8-2: dsPIC30F4013 INTERRUPT
VECTOR TABLE
INT Vector
Number Number
Interrupt Source
Highest Natural Order Priority
0
8 INT0 – External Interrupt 0
1
9 IC1 – Input Capture 1
2
10 OC1 – Output Compare 1
3
11 T1 – Timer 1
4
12 IC2 – Input Capture 2
5
13 OC2 – Output Compare 2
6
14 T2 V Timer 2
7
15 T3 – Timer 3
8
16 SPI1
9
17 U1RX – UART1 Receiver
10
18 U1TX – UART1 Transmitter
11
19 ADC – ADC Convert Done
12
20 NVM – NVM Write Complete
13
21 SI2C – I2C™ Slave Interrupt
14
22 MI2C – I2C Master Interrupt
15
23 Input Change Interrupt
16
24 INT1 – External Interrupt 1
17
25 IC7 – Input Capture 7
18
26 IC8 – Input Capture 8
19
27 OC3 – Output Compare 3
20
28 OC4 – Output Compare 4
21
29 T4 – Timer 4
22
30 T5 – Timer 5
23
31 INT2 – External Interrupt 2
24
32 U2RX – UART2 Receiver
25
33 U2TX – UART2 Transmitter
26
34 Reserved
27
35 C1 – Combined IRQ for CAN1
28-40 36-48 Reserved
41
49 DCI – CODEC Transfer Done
42
50 LVD – Low-Voltage Detect
43-53 51-61 Reserved
Lowest Natural Order Priority
dsPIC30F3014/4013
8.2 Reset Sequence
A Reset is not a true exception because the interrupt
controller is not involved in the Reset process. The pro-
cessor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
8.2.1 RESET SOURCES
In addition to external Reset and Power-on Reset
(POR), these sources of error conditions ‘trap’ to the
Reset vector:
• Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer causes a Reset.
• Illegal Instruction Trap:
Attempted execution of any unused opcodes
results in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
• Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
• Trap Lockout:
Occurrence of multiple trap conditions
simultaneously causes a Reset.
© 2007 Microchip Technology Inc.
DS70138E-page 57
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