MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name

Description

Manufacturer

MT90866

Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch

Zarlink Semiconductor Inc 

MT90866

Data Sheet

In primary master mode the jitter attenuation of the DPLL is determined by the internal 1.52 Hz low pass Loop Filter

and the Phase Slope Limiter. Figure 17, "DPLL Jitter Transfer Function Diagram - wide range of frequencies" on

page 42 shows the DPLL jitter transfer function diagram in a wide range of frequencies, while Figure 18, "Detailed

DPLL Jitter Transfer Function Diagram" on page 43 is the portion of the diagram from Figure 17 around 0 dB of the

jitter transfer amplitude. At this point it is possible to see that when operating in primary master mode the DPLL is a

second order, type 2 PLL. The jitter transfer function can be described as a low pass filter to 1.52 Hz,

-20 dB/decade, with peaking less then 0.5 dB.

All outputs are derived from the same signal, therefore these diagrams apply to all outputs. Since 1U.I. at

1.544 MHz (648 nsPP) is not equal to 1 U.I. at 2.048 MHz (488 nsPP). a transfer value using different input and

output frequencies must be calculated in common units (e.g., seconds) as shown in the following example:

What is the T1 and E1 output jitter when the T1 input jitter is 20 U.I. (T1 U.I. Units) and the T1 to T1 jitter attenuation

is 18 dB, for a given jittering frequency?





–-2---A0--

OutputT1 = InputT1×10





–--2--1-0--8-

OutputT1 = 20×10

= 2.5UI(T1)

OutputE1

=

OutputT1

×

-(--1---U-----I---T---1----)

(1UIE1)

OutputE1 = OutputT1 × ((---64---48---48---nn----ss---))= 3.3UI(T1)

Using the method mentioned above, the jitter attenuation can be calculated for all combinations of inputs and

outputs.

Because intrinsic jitter is always present, the jitter attenuation will appear to be lower for small input jitter signals

than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input

jitter signals (e.g., 75% of the specified maximum jitter tolerance).

Figure 17 - DPLL Jitter Transfer Function Diagram - wide range of frequencies

42

Zarlink Semiconductor Inc.

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