MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name

Description

Manufacturer

MT90866

Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch

Zarlink Semiconductor Inc 

MT90866

Data Sheet

Bit

Name

Description

8-6 LG22-LG20 Local Group 2 Mode Select: These three bits refer to different switching mode for

group 2 (STi8-11 and STo8-11) of the local interface.

LG22

0

0

0

0

1

LG21

0

0

1

1

0

LG20

0

1

0

1

0

Switching Mode

8 Mb/s

4 Mb/s

2 Mb/s

4-bit wide subrate

2-bit wide subrate

Usable Streams

STi8-11, STo8-11

STi8-11, STo8-11

STi8-11, STo8-11

STi8-11, STo8-11

STi8-11, STo8-11

5-3 LG12-LG10 Local Group 1 Mode Select: These three bits refer to different switching modes for

group 1 (STi4-7 and STo4-7) of the local interface.

LG12

0

0

0

0

1

LG11

0

0

1

1

0

LG10

0

1

0

1

0

Switching Mode

8 Mb/s

4 Mb/s

2 Mb/s

4-bit wide subrate

2-bit wide subrate

Usable Streams

STi4-7, STo4-7

STi4-7, STo4-7

STi4-7, STo4-7

STi4-7, STo4-7

STi4-7, STo4-7

2-0 LG02-LG00 Local Group 0 Mode Select: These three bits refer to different switching modes for

group 0 (STi0-3 and STo0-3) of the local interface.

LG02

0

0

0

0

1

LG01

0

0

1

1

0

LG00

0

1

0

1

0

Switching Mode

8 Mb/s

4 Mb/s

2 Mb/s

4-bit wide subrate

2-bit wide subrate

Usable Streams

STi0-3, STo0-3

STi0-3, STo0-3

STi0-3, STo0-3

STi0-3, STo0-3

STi0-3, STo0-3

Table 10 - Device Mode Selection (DMS) Register Bits (continued)

Read/Write Address: 0002H

Reset Value: 0000H

15 14 13 12 11 10 9

8

0 0 0 0 0 0 0 BBPD2

7

BBPD1

6

BBPD0

5

LBPD2

4

LBPD1

3

LBPD0

2

10

BPE 0 0

Bit Name

Description

15-9 Unused Reserved. In functional mode, these bits MUST be low.

8-6 BBPD2-0 Backplane Block Programming Data Bits: These bits carry the value to be loaded into

the backplane connection memory block whenever the Memory Block Programming feature

is activated. After the MBP bit in the control register is set to high and the BPE is set to high,

the contents of the bits BBPD2 - 0 are loaded into bits 15 - 13 of the backplane connection

memory. Bits 12 - 0 of the backplane connection memory are programmed to be zero.

Table 11 - Block Programming Mode (BPM) Register Bits

48

Zarlink Semiconductor Inc.

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