MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
Manufacturer
MT90866
Zarlink Semiconductor Inc
MT90866 Datasheet PDF : 86 Pages
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MT90866
Data Sheet
Figure 18 - Detailed DPLL Jitter Transfer Function Diagram
19.4 Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock signal when the DPLL is not locked to
an external reference, but is operating in the Freerun Mode. Because the output of the DCO Circuit has only
discrete values, the output frequency of the DPLL has the limited accuracy of 0.03 ppm based upon the design
implementation. In addition, the master clock (C20i) accuracy also directly affects the freerun accuracy. The freerun
accuracy is then, 0.03 ppm plus the master clock accuracy.
19.5 Holdover Frequency Stability
Holdover frequency stability is defined as the maximum fractional frequency offset of an output clock signal when it
is operating using a stored frequency value. For the DPLL, the stored value is determined while the device is in
Normal Mode and locked to an external reference signal. As a result, when the DPLL is in the Normal Mode, the
stability of the master clock (C20i) does not affect the holdover frequency stability because the DPLL will
compensate for master clock changes while in Normal Mode. However, when the DPLL is in the Holdover Mode,
the stability of the master clock does affect the Holdover frequency stability. The holdover frequency stability is
0.07 ppm assuming that the C20i frequency is held constant.
19.6 Locking Range
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to
maintain the synchronization. The locking range is defined by the Loop Filter Circuit and is equal to +/- 298 ppm.
Note that the locking range is related to the master clock (C20i). If the master clock is shifted by -100 ppm, the
whole locking range also shifts -100 ppm downwards to be: -398 ppm to 198 ppm.
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