NXP Semiconductors
PCA85176
Universal LCD driver for low multiplex rates
10. Static characteristics
Table 16. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = −40 °C to +95 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Supplies
VDD
VLCD
IDD
IDD(LCD)
Logic
supply voltage
LCD supply voltage
supply current
LCD supply current
fclk(ext) = 1536 Hz
fclk(ext) = 1536 Hz
1.8
-
5.5
[1]
2.5
-
8.0
[2][3] -
-
20
[2][4] -
-
60
VP(POR)
VIL
power-on reset supply voltage
LOW-level input voltage
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
1.0
1.3
VSS
-
1.6
0.3VDD
VIH
HIGH-level input voltage
on pins CLK, SYNC,
[5][6] 0.7VDD -
VDD
OSC, A0 to A2, SA0,
SCL, SDA
IOL
LOW-level output current
output sink current;
VOL = 0.4 V; VDD = 5 V
on pins CLK and SYNC
1
-
-
on pin SDA
3
-
-
IOH(CLK)
IL
HIGH-level output current on pin CLK
leakage current
output source current;
VOH = 4.6 V; VDD = 5 V
VI = VDD or VSS;
on pins CLK, SCL, SDA,
A0 to A2 and SA0
1
-
-
−1
-
+1
IL(OSC)
leakage current on pin OSC
CI
input capacitance
LCD outputs
VI = VDD
−1
-
+1
[7]
-
-
7
ΔVO
output voltage variation
on pins BP0 to BP3 and
S0 to S39
−100 -
+100
RO
output resistance
VLCD = 5 V
[8]
on pins BP0 to BP3
-
1.5
-
on pins S0 to S39
-
6.0
-
Unit
V
V
μA
μA
V
V
V
mA
mA
mA
μA
μA
pF
mV
kΩ
kΩ
[1] VLCD > 3 V for 1⁄3 bias.
[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[3] For typical values, see Figure 19.
[4] For typical values, see Figure 20.
[5] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 15 (see Figure 18
as well).
[6] Propagation delay of driver between clock (CLK) and LCD driving signals.
[7] Periodically sampled, not 100 % tested.
[8] Outputs measured one at a time.
PCA85176_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 14 April 2010
© NXP B.V. 2010. All rights reserved.
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