ST7PSCR1E4M1/XXX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7PSCR1E4M1/XXX
STMicroelectronics
ST7PSCR1E4M1/XXX Datasheet PDF : 102 Pages
| |||
ST7SCR
TIMEBASE UNIT (Cont’d)
12.2.5 Low Power Modes
Mode
WAIT
HALT
Description
No effect on TBU
TBU halted.
12.2.6 Interrupts
Interrupt
Event
Counter Over-
flow Event
Event
Flag
Enable
Control
Bit
OVF ITE
Exit
from
Wait
Yes
Exit
from
Halt
No
Note: The OVF interrupt event is connected to an
interrupt vector (see Interrupts chapter).
It generates an interrupt if the ITE bit is set in the
TBUCSR register and the I-bit in the CC register is
reset (RIM instruction).
12.2.7 Register Description
TBU COUNTER VALUE REGISTER (TBUCV)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
CV7 CV6 CV5 CV4 CV3 CV2 CV1 CV0
TBU CONTROL/STATUS REGISTER (TBUCSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0 0 OVF ITE TCEN PR2 PR1 PR0
Bits [7:6] = Reserved. Forced by hardware to 0.
Bit 5 = OVF Overflow Flag
This bit is set only by hardware, when the counter
value rolls over from FFh to 00h. It is cleared by
software reading the TBUCSR register. Writing to
this bit does not change the bit value.
0: No overflow
1: Counter overflow
Bit 4 = ITE Interrupt enabled.
This bit is set and cleared by software.
0: Overflow interrupt disabled
1: Overflow interrupt enabled. An interrupt request
is generated when OVF=1.
Bit 3 = TCEN TBU Enable.
This bit is set and cleared by software.
0: TBU counter is frozen and the prescaler is reset.
1: TBU counter and prescaler running.
Bits 7:0 = CV[7:0] Counter Value
This register contains the 8-bit counter value
which can be read and written anytime by soft-
ware. It is continuously incremented by hardware if
TCEN=1.
Bits 2:0 = PR[2:0] Prescaler Selection
These bits are set and cleared by software to se-
lect the prescaling factor.
PR2 PR1 PR0
000
001
010
011
100
101
110
111
Prescaler Division Factor
2
4
8
16
32
64
128
256
43/102
1
Share Link: 