PCF8578HT View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCF8578HT Datasheet PDF : 46 Pages
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NXP Semiconductors
PCF8578
LCD row/column driver for dot matrix graphic displays
8.5 Oscillator
8.5.1 Internal clock
The clock signal for the system may be generated by the internal oscillator and prescaler.
The frequency is determined by the value of the resistor Rext(OSC), see Figure 10. For
normal use a value of 330 kΩ is recommended. The clock signal, for cascaded
PCF8579s, is output at CLK and has a frequency of 1⁄6 (multiplex rate 1:8, 1:16 and 1:32)
or 1⁄8 (multiplex rate 1:24) of the oscillator frequency.
103
fosc
(kHz)
102
msa837
10
1
10
102
103
104
Rext(OSC) (kΩ)
To avoid capacitive coupling, which could adversely affect oscillator stability, Rext(OSC) should be
placed as closely as possible to the OSC pin. If this proves to be a problem, a filtering capacitor
may be connected in parallel to Rext(OSC).
Fig 10. Oscillator frequency as a function of external oscillator resistor, Rext(OSC)
8.5.2 External clock
If an external clock is used, OSC must be connected to VDD and the external clock signal
to CLK. Table 8 summarizes the nominal CLK and SYNC frequencies.
Table 8. Signal frequencies required for nominal 64 Hz frame frequency[1]
Oscillator frequency,
fosc (Hz)[2]
12 288
Frame frequency,
ffr (Hz)
64
Multiplex rate, Division ratio
(1:n)
1:8, 1:16, 1:32 6
Clock frequency,
fclk (Hz)
2 048
12 288
64
1:24
8
1 536
[1] A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
[2] Rext(OSC) = 330 kΩ.
8.6 Timing generator
The timing generator of the PCF8578 organizes the internal data flow of the device and
generates the LCD frame synchronization pulse SYNC, whose period is an integer
multiple of the clock period. In cascaded applications, this signal maintains the correct
timing relationship between the PCF8578 and PCF8579s in the system.
PCF8578_6
Product data sheet
Rev. 06 — 5 May 2009
© NXP B.V. 2009. All rights reserved.
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