PCF8578HT View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

PCF8578HT

LCD row/column driver for dot matrix graphic displays

NXP Semiconductors. 

NXP Semiconductors

PCF8578

LCD row/column driver for dot matrix graphic displays

START

condition

SCL FROM

MASTER

1

2

clock pulse for

acknowledgement

8

9

DATA OUTPUT

BY TRANSMITTER

S

DATA OUTPUT

BY RECEIVER

mba606

The general characteristics and detailed specification of the I2C-bus are available on request.

Fig 14. Acknowledgement on the I2C-bus

8.8.5 I2C-bus controller

The I2C-bus controller detects the I2C-bus protocol, slave address, commands and display

data bytes. It performs the conversion of the data input (serial-to-parallel) and the data

output (parallel-to-serial). The PCF8578 acts as an I2C-bus slave transmitter/receiver in

mixed mode, and as a slave receiver in row mode. A slave device cannot control bus

communication.

8.8.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

8.8.7 I2C-bus protocol

Two 7-bit slave addresses (0111 100 and 0111 101) are reserved for both the PCF8578

and PCF8579. The least significant bit of the slave address is set by connecting input SA0

to either logic 0 (VSS) or logic 1 (VDD). Therefore, two types of PCF8578 or PCF8579 can

be distinguished on the same I2C-bus which allows:

1. One PCF8578 to operate with up to 32 PCF8579s on the same I2C-bus for very large

applications.

2. The use of two types of LCD multiplex schemes on the same I2C-bus.

In most applications the PCF8578 will have the same slave address as the PCF8579.

The I2C-bus protocol is shown in Figure 15. All communications are initiated with a START

condition (S) from the I2C-bus master, which is followed by the desired slave address and

read/write bit. All devices with this slave address acknowledge in parallel. All other devices

ignore the bus transfer.

In WRITE mode (indicated by setting the read/write bit LOW) one or more commands

follow the slave address acknowledgement. The commands are also acknowledged by all

addressed devices on the bus. The last command must clear the continuation bit C.

After the last command a series of data bytes may follow. The acknowledgement after

each byte is made only by the (A0, A1, A2 and A3) addressed PCF8579 or PCF8578 with

its implicit subaddress 0. After the last data byte has been acknowledged, the I2C-bus

master issues a STOP condition (P).

PCF8578_6

Product data sheet

Rev. 06 — 5 May 2009

© NXP B.V. 2009. All rights reserved.

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