PCF8578HT View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

PCF8578HT

LCD row/column driver for dot matrix graphic displays

NXP Semiconductors. 

NXP Semiconductors

PCF8578

LCD row/column driver for dot matrix graphic displays

8.8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each data byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse. A slave receiver

which is addressed must generate an acknowledge after the reception of each byte. Also

a master must generate an acknowledge after the reception of each byte that has been

clocked out of the slave transmitter. The device that acknowledges must pull down the

SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during

the HIGH period of the acknowledge related clock pulse (set-up and hold times must be

taken into consideration). A master receiver must signal the end of a data transmission to

the transmitter by not generating an acknowledge on the last byte that has been clocked

out of the slave. In this event the transmitter must leave the data line HIGH to enable the

master to generate a STOP condition.

SDA

SCL

Fig 11. Bit transfer

data line

stable;

data valid

change

of data

allowed

mba607

SDA

SCL

S

START condition

Fig 12. Definition of START and STOP condition

P

STOP condition

mba608

SDA

SCL

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER

Fig 13. System configuration

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

mba605

PCF8578_6

Product data sheet

Rev. 06 — 5 May 2009

© NXP B.V. 2009. All rights reserved.

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