PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LC658-I/CL

High-Performance Microcontrollers with CAN Module

Microchip Technology 

PIC18CXX8

TABLE 4-3: REGISTER FILE SUMMARY

Filename

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS(3)

TOSU

—

—

—

Top-of-Stack upper Byte (TOS<20:16>)

---0 0000 ---0 0000

TOSH

Top-of-Stack High Byte (TOS<15:8>)

0000 0000 0000 0000

TOSL

Top-of-Stack Low Byte (TOS<7:0>)

0000 0000 0000 0000

STKPTR

PCLATU

STKFUL

—

STKUNF

—

—

bit 21(3)

Return Stack Pointer

Holding Register for PC<20:16>

00-0 0000 00-0 0000

--00 0000 --00 0000

PCLATH

Holding Register for PC<15:8>

0000 0000 0000 0000

PCL

TBLPTRU

PC Low Byte (PC<7:0>)

—

—

bit 21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

0000 0000 0000 0000

---0 0000 ---0 0000

TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

0000 0000 0000 0000

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

0000 0000 0000 0000

TABLAT

Program Memory Table Latch

0000 0000 0000 0000

PRODH

Product Register High Byte

xxxx xxxx uuuu uuuu

PRODL

Product Register Low Byte

xxxx xxxx uuuu uuuu

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF 0000 000x 0000 000u

INTCON2 RBPU

INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP

INT3IP

RBIP 1111 1111 1111 1111

INTCON3 INT2IP

INT1IP

INT3IE

INT2IE

INT1IE

INT3IF

INT2IF

INT1IF 1100 0000 1100 0000

INDF0

Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)

n/a

n/a

POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)

n/a

n/a

POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)

n/a

n/a

PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)

n/a

n/a

PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value

n/a

n/a

of FSR0 offset by WREG

FSR0H

—

—

—

—

Indirect Data Memory Address Pointer 0 High

---- 0000 ---- 0000

FSR0L

Indirect Data Memory Address Pointer 0 Low Byte

xxxx xxxx uuuu uuuu

WREG

Working Register

xxxx xxxx uuuu uuuu

INDF1

Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)

n/a

n/a

POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)

n/a

n/a

POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)

n/a

n/a

PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)

n/a

n/a

PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value

n/a

n/a

of FSR1 offset by WREG

FSR1H

—

—

—

—

Indirect Data Memory Address Pointer 1 High

---- 0000 ---- 0000

FSR1L

Indirect Data Memory Address Pointer 1 Low Byte

xxxx xxxx uuuu uuuu

BSR

—

—

—

—

Bank Select Register

---- 0000 ---- 0000

Legend:

Note 1:

2:

3:

4:

x = unknown, u = unchanged, - = unimplemented, q = value depends on condition

Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.

Bit 21 of the TBLPTRU allows access to the device configuration bits.

Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.

These registers are reserved on PIC18C658.

DS30475A-page 52

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 2000 Microchip Technology Inc.

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