PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LC658-I/CL Datasheet PDF : 366 Pages
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PIC18CXX8
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS(3)
CCPR1H
CCPR1L
CCP1CON
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
—
—
DC1B1
DC1B0
CCPM3
CCP1M2
CCP1M1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M0 --00 0000 --00 0000
CCPR2H
CCPR2L
CCP2CON
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
—
—
DC2B1
DC2B0
CCPM3
CCP2M2
CCP2M1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M0 0000 0000 0000 0000
VRCON
CMCON
TMR3H
TMR3L
T3CON
PSPCON
VREN
VROEN
C2OUT
C1OUT
Timer3 Register High Byte
Timer3 Register Low Byte
RD16
T3CCP2
IBF
OBF
VRR
C2INV
T3CKPS1
IBOV
VRSS
C1INV
T3CKPS0
PSPMODE
VR3
CIS
T3CCP1
—
VR2
CM2
T3SYNC
—
VR1
CM1
TMR3CS
—
VR0
0000 0000 0000 0000
CM0 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR3ON 0000 0000 uuuu uuuu
—
0000 ---- 0000 ----
SPBRG
RCREG
TXREG
TXSTA
USART Baud Rate Generator
USART Receive Register
USART Transmit Register
CSRC
TX9
TXEN
SYNC
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
RCSTA
IPR3
PIR3
PIE3
IPR2
SPEN
IRXIP
IRXIF
IRXIE
—
RX9
WAKIP
WAKIF
WAKIE
CMIP
SREN
ERRIP
ERRIF
ERRIE
—
CREN
TXB2IP
TXB2IF
TXB2IE
—
ADEN
TXB1IP
TXB1IF
TXB1IE
BCLIP
FERR
TXB0IP
TXB0IF
TXB0IE
LVDIP
OERR
RXB1IP
RXB1IF
RXB1IE
TMR3IP
RX9D
RXB0IP
RXB0IF
RXB0IE
CCP2IP
0000 000x 0000 000x
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
-1-- 1111 -1-- 1111
PIR2
—
CMIF
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF -0-- 0000 -0-- 0000
PIE2
—
CMIE
—
—
BCLIE
LVDIE
TMR3IE CCP2IE -0-- 0000 -0-- 0000
IPR1
PIR1
PIE1
TRISJ(4)
TRISH(4)
TRISG
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
Data Direction Control Register for PORTJ
Data Direction Control Register for PORTH
—
—
—
Data Direction Control Register for PORTG
TMR1IP
TMR1IF
TMR1IE
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
---1 1111 ---1 1111
TRISF
Data Direction Control Register for PORTF
1111 1111 1111 1111
TRISE
Data Direction Control Register for PORTE
1111 1111 1111 1111
TRISD
Data Direction Control Register for PORTD
1111 1111 1111 1111
TRISC
Data Direction Control Register for PORTC
1111 1111 1111 1111
TRISB
TRISA
Data Direction Control Register for PORTB
—
Bit 6(1) Data Direction Control Register for PORTA
1111 1111 1111 1111
--11 1111 --11 1111
Legend:
Note 1:
2:
3:
4:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
These registers are reserved on PIC18C658.
DS30475A-page 54
Advanced Information
2000 Microchip Technology Inc.
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