PIC18CXX8
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS(3)
TXB0D7
TXB0D6
TXB0D5
TXB0D4
TXB0D3
TXB0D2
TXB0D1
TXB0D0
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
TXB0D77
TXB0D67
TXB0D57
TXB0D47
TXB0D37
TXB0D27
TXB0D17
TXB0D07
—
EID7
EID15
SID2
SID10
—
TXB0D76
TXB0D66
TXB0D56
TXB0D46
TXB0D36
TXB0D26
TXB0D16
TXB0D06
TXRTR
EID6
EID14
SID1
SID9
TXABT
TXB0D75
TXB0D65
TXB0D55
TXB0D45
TXB0D35
TXB0D25
TXB0D15
TXB0D05
—
EID5
EID13
SID0
SID8
TXLARB
TXB0D74
TXB0D64
TXB0D54
TXB0D44
TXB0D34
TXB0D24
TXB0D14
TXB0D04
—
EID4
EID12
—
SID7
TXERR
TXB0D73
TXB0D63
TXB0D53
TXB0D43
TXB0D33
TXB0D23
TXB0D13
TXB0D03
DLC3
TXB0D72
TXB0D62
TXB0D52
TXB0D42
TXB0D32
TXB0D22
TXB0D12
TXB0D02
DLC2
EID3
EID11
EXIDEN
SID6
TXREQ
EID2
EID10
—
SID5
—
TXB0D71
TXB0D61
TXB0D51
TXB0D41
TXB0D31
TXB0D21
TXB0D11
TXB0D01
DLC1
EID1
EID9
EID17
SID4
TXPRI1
TXB0D70
TXB0D60
TXB0D50
TXB0D40
TXB0D30
TXB0D20
TXB0D10
TXB0D00
DLC0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0x00 xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0u00 uuuu
EID0
EID8
EID16
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx0 x0xx uuu0 u0uu
SID3
TXPRI0
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
CANSTAT
TXB1D7
TXB1D6
TXB1D5
TXB1D4
TXB1D3
TXB1D2
TXB1D1
TXB1D0
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
OPMODE2
TXB1D77
TXB1D67
TXB1D57
TXB1D47
TXB1D37
TXB1D27
TXB1D17
TXB1D07
—
EID7
EID15
SID2
OPMODE1
TXB1D76
TXB1D66
TXB1D56
TXB1D46
TXB1D36
TXB1D26
TXB1D16
TXB1D06
TXRTR
EID6
EID14
SID1
OPMODE0
TXB1D75
TXB1D65
TXB1D55
TXB1D45
TXB1D35
TXB1D25
TXB1D15
TXB1D05
—
EID5
EID13
SID0
SID10
—
SID9
TXABT
SID8
TXLARB
—
TXB1D74
TXB1D64
TXB1D54
TXB1D44
TXB1D34
TXB1D24
TXB1D14
TXB1D04
—
EID4
EID12
—
SID7
TXERR
ICODE2
TXB1D73
TXB1D63
TXB1D53
TXB1D43
TXB1D33
TXB1D23
TXB1D13
TXB1D03
DLC3
ICODE1
TXB1D72
TXB1D62
TXB1D52
TXB1D42
TXB1D32
TXB1D22
TXB1D12
TXB1D02
DLC2
EID3
EID11
EXIDE
SID6
TXREQ
EID2
EID10
—
SID5
—
ICODE0
TXB1D71
TXB1D61
TXB1D51
TXB1D41
TXB1D31
TXB1D21
TXB1D11
TXB1D01
DLC1
EID1
EID9
EID17
SID4
TXPRI1
—
xxx- xxx- uuu- uuu-
TXB1D70
TXB1D60
TXB1D50
TXB1D40
TXB1D30
TXB1D20
TXB1D10
TXB1D00
DLC0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0x00 xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0u00 uuuu
EID0
EID8
EID16
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx0 x0xx uuu0 u0uu
SID3
TXPRI0
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
CANSTAT OPMODE2 OPMODE1 OPMODE0
—
ICODE2 ICODE1
ICODE0
—
xxx- xxx- uuu- uuu-
Legend:
Note 1:
2:
3:
4:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
These registers are reserved on PIC18C658.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 57