PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LC658-I/CL

High-Performance Microcontrollers with CAN Module

Microchip Technology 

PIC18CXX8

Filename

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS(3)

INDF2

Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)

n/a

n/a

POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)

n/a

n/a

POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)

n/a

n/a

PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)

n/a

n/a

PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value

n/a

n/a

of FSR2 offset by WREG

FSR2H

—

—

—

—

Indirect Data Memory Address Pointer 2 High

---- 0000 ---- 0000

FSR2L

Indirect Data Memory Address Pointer 2 Low Byte

xxxx xxxx uuuu uuuu

STATUS

—

—

—

N

OV

Z

DC

C

---x xxxx ---u uuuu

TMR0H

TMR0L

T0CON

OSCCON

Timer0 register high byte

Timer0 register low byte

TMR0ON

T08BIT

—

—

T0CS

—

T0SE

—

T0PS3

—

T0PS2

—

T0PS1

—

T0PS0

SCS

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

---- ---0 ---- ---0

LVDCON

—

—

IRVST

LVDEN

LVDL3

LVDL2

LVDL1

LVDL0 --00 0101 --00 0101

WDTCON

—

—

—

—

—

—

—

SWDTEN ---- ---0 ---- ---0

RCON

IPEN

LWRT

—

RI

TO

PD

POR

BOR 00-1 11qq 00-q qquu

TMR1H

TMR1L

T1CON

Timer1 Register High Byte

Timer1 Register Low Byte

RD16

—

T1CKPS1

T1CKPS0 T1OSCEN T1SYNC

TMR1CS

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

TMR1ON 0-00 0000 u-uu uuuu

TMR2

PR2

T2CON

Timer2 Register

Timer2 Period Register

—

TOUTPS3

TOUTPS2

TOUTPS1 TOUTPS0 TMR2ON

T2CKPS1

0000 0000 0000 0000

1111 1111 1111 1111

T2CKPS0 -000 0000 -000 0000

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

ADCON0

SSP Receive Buffer/Transmit Register

SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode.

SMP

CKE

D/A

P

S

R/W

UA

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

GCEN

ACKSTAT

ACKDT

ACKEN

RCEN

PEN

RSEN

A/D Result Register High Byte

A/D Result Register Low Byte

—

—

CHS3

CHS2

CHS1

CHS0

GO/DONE

BF

SSPM0

SEN

ADON

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

--00 0000 --00 0000

ADCON1

—

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0 -000 0000 -000 0000

ADCON2

ADFM

—

—

—

—

ADCS2

ADCS1

ADCS0 0--- -000 0--- -000

Legend:

Note 1:

2:

3:

4:

x = unknown, u = unchanged, - = unimplemented, q = value depends on condition

Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.

Bit 21 of the TBLPTRU allows access to the device configuration bits.

Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.

These registers are reserved on PIC18C658.

 2000 Microchip Technology Inc.

Advanced Information

DS30475A-page 53

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