PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LC658-I/CL

High-Performance Microcontrollers with CAN Module

Microchip Technology 

PIC18CXX8

Filename

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS(3)

LATJ(4)

LATH(4)

Read PORTJ Data Latch, Write PORTJ Data Latch

Read PORTH Data Latch, Write PORTH Data Latch

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

LATG

—

—

—

Read PORTG Data Latch, Write PORTG Data Latch

---x xxxx ---u uuuu

LATF

Read PORTF Data Latch, Write PORTF Data Latch

xxxx xxxx uuuu uuuu

LATE

Read PORTE Data Latch, Write PORTE Data Latch

xxxx xxxx uuuu uuuu

LATD

Read PORTD Data Latch, Write PORTD Data Latch

xxxx xxxx uuuu uuuu

LATC

Read PORTC Data Latch, Write PORTC Data Latch

xxxx xxxx uuuu uuuu

LATB

LATA

PORTJ(4)

PORTH(4)

Read PORTB Data Latch, Write PORTB Data Latch

—

Bit 6(1) Read PORTA Data Latch, Write PORTA Data Latch

Read PORTJ pins, Write PORTJ Data Latch

Read PORTH pins, Write PORTH Data Latch

xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

PORTG

—

—

—

Read PORTG pins, Write PORTG Data Latch

---x xxxx uuuu uuuu

PORTF

Read PORTF pins, Write PORTF Data Latch

0000 0000 0000 0000

PORTE

Read PORTE pins, Write PORTE Data Latch

xxxx xxxx uuuu uuuu

PORTD

Read PORTD pins, Write PORTD Data Latch

xxxx xxxx uuuu uuuu

PORTC

Read PORTC pins, Write PORTC Data Latch

xxxx xxxx uuuu uuuu

PORTB

Read PORTB pins, Write PORTB Data Latch

PORTA

—

Bit 6(1) Read PORTA pins, Write PORTA Data Latch

TRISK(4)

Data Direction Control Register for PORTK

LATK(4)

Read PORTK Data Latch, Write PORTK Data Latch

PORTK(4) Read PORTK pins, Write PORTK Data Latch

TXERRCNT

TEC7

TEC6

TEC5

TEC4

TEC3

TEC2

RXERRCNT REC7

REC6

COMSTAT RXB0OVFL RXB1OVFL

CIOCON

TX1SRC

TX1EN

BRGCON3

—

WAKFIL

BRGCON2 SEG2PHTS

SAM

BRGCON1

SJW1

SJW0

REC5

TXBO

ENDRHI

—

SEG1PH2

BRP5

REC4

TXBP

CANCAP

—

SEG1PH1

BRP4

REC3

RXBP

—

—

SEG1PH0

BRP3

REC2

TXWARN

—

SEG2PH2

PRSEG2

BRP2

TEC1

REC1

RXWARN

—

SEG2PH1

PRSEG1

BRP1

xxxx xxxx uuuu uuuu

--0x 0000 --0u 0000

1111 1111 1111 1111

xxxx xxxx uuuu uuuu

TEC0

REC0

EWARN

—

SEG2PH0

PRSEG0

BRP0

xxxx xxxx

0000 0000

0000 0000

0000 0000

1000 ----

-0-- -000

0000 0000

0000 0000

uuuu uuuu

0000 0000

0000 0000

0000 0000

1000 ----

-0-- -000

0000 0000

0000 0000

CANCON

REQOP2 REQOP1 REQOP0

ABAT

WIN2

WIN1

WIN0

—

xxxx xxx- uuuu uuu-

CANSTAT OPMODE2 OPMODE1 OPMODE0

—

ICODE2 ICODE1

ICOED0

—

xxx- xxx- uuu- uuu-

Legend:

Note 1:

2:

3:

4:

x = unknown, u = unchanged, - = unimplemented, q = value depends on condition

Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.

Bit 21 of the TBLPTRU allows access to the device configuration bits.

Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.

These registers are reserved on PIC18C658.

 2000 Microchip Technology Inc.

Advanced Information

DS30475A-page 55

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