STA335W View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA335W Datasheet PDF : 43 Pages
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Register description
STA335W
Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI
SAI [3:0]
SAIFB
Interface Format
32 * fs
1100
1110
0100
0100
1000
1100
1
I2S 15-bit data
1
Left/right-justified 16-bit data
1
I2S 23-bit data
1
I2S 20-bit data
1
I2S 18-bit data
1
LSB first I2S 16-bit data
0001
1
Left-justified 24-bit data
48 * fs
0101
1001
1
Left-justified 20-bit data
1
Left-justified 18-bit data
1101
1
Left-justified 16-bit data
0010
1
Right-justified 24-bit data
0110
1
Right-justified 20-bit data
1010
1
Right-justified 18-bit data
1110
0000
0100
1000
1100
1
Right-justified 16-bit data
1
I2S 24-bit data
1
I2S 20-bit data
1
I2S 18-bit data
1
LSB first I2S 16-bit data
0001
1
Left-justified 24-bit data
64 * fs
0101
1001
1
Left-justified 20-bit data
1
Left-justified 18-bit data
1101
1
Left-justified 16-bit data
0010
1
Right-justified 24-bit data
0110
1
Right-justified 20-bit data
1010
1
Right-justified 18-bit data
1110
1
Right-justified 16-bit data
To make the STA335W work properly, the serial audio interface LRCKI clock must be
synchronous to the PLL output clock. It means that:
■ the frequency of PLL clock / frequency of LRCKI = N ±4 cycles,
where N depends on the settings in Table 13 on page 19
■ the PLL must be locked.
If these two conditions are not met, and IDE bit (reg 0x05 bit 2) is set to 1, the STA335W will
immediately mute the I2S PCM data out (provided to the processing block) and it will freeze
any active processing task.
To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any
audio streams flowing into STA335W data path before the desynchronization event
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