Register description
STA335W
5.3
Configuration register C (addr 0x02)
5.3.1
5.3.2
D7
D6
D5
D4
D3
D2
D1
D0
OCRB
CSZ3
CSZ2
CSZ1
CSZ0
OM1
OM0
1
0
1
1
1
1
1
FFX power output mode
Table 22. FFX power output mode
Bit R/W RST
Name
Description
0
R/W
1
1
R/W
1
OM0
OM1
Selects configuration of FFX output.
The FFX power output mode selects how the FFX output timing is configured.
Different power devices use different output modes.
Table 23. Output modes
OM[1,0]
Output stage mode
00
Drop compensation
01
Discrete output stage - tapered compensation
10
Full power mode
11
Variable drop compensation (CSZx bits)
FFX compensating pulse size register
Table 24. FFX compensating pulse size bits
Bit R/W RST
Name
Description
2
R/W
1
3
R/W
1
4
R/W
1
5
R/W
0
CSZ0
CSZ1
CSZ2
CSZ3
When OM[1,0] = 11, this register determines the size
of the FFX compensating pulse from 0 clock ticks to
15 clock periods.
Table 6:
Table 25. Compensating pulse size
CSZ[3:0]
Compensating Pulse Size
0000
0001
…
1111
0 ns (0 tick) compensating pulse size
20 ns (1 tick) clock period compensating pulse size
…
300 ns (15 tick) clock period compensating pulse size
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