STA335W View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA335W Datasheet PDF : 43 Pages
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Register description
STA335W
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Invalid input detect mute enable
Table 37. Invalid input detect mute enable
Bit R/W RST
Name
Description
2
R/W
1
IDE
Setting of 1 enables the automatic invalid input
detect mute
Setting the IDE bit enables this function, which looks at the input I2S data and automatically
mutes if the signals are perceived as invalid.
Binary output mode clock loss detection
Table 38. Binary output mode clock loss detection
Bit R/W RST
Name
Description
3
R/W
1
BCLE
Binary output mode clock loss detection enable
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
Table 39. LRCK double trigger protection
Bit R/W RST
Name
Description
4
R/W
1
LDTE
LRCLK double trigger protection enable
Actively prevents double trigger of LRCLK.
Auto EAPD on clock loss
Table 40. Auto EAPD on clock loss
Bit R/W RST
Name
Description
5
R/W
0
ECLE
Auto EAPD on clock loss
When active, issues a power device power down signal (EAPD) on clock loss detection.
IC power down
Table 41. IC power down
Bit R/W RST
Name
Description
6
R/W
1
PWDN
0: IC power down low-power condition
1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power-stage, then the master clock to all internal hardware expect the
I2C block is gated. This places the IC in a very low power consumption state.
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