STA335BWS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA335BWS Datasheet PDF : 68 Pages
| |||
STA335BWS
Register description
6.1
Configuration register A (addr 0x00)
D7
D6
D5
D4
FDRB
TWAB
TWRB
IR1
0
1
1
0
6.1.1 Master clock select
D3
D2
D1
D0
IR0
MCS2
MCS1
MCS0
0
0
1
1
Bit
R/W
RST
Name
Description
0
R/W
1
1
R/W
1
2
R/W
0
MCS0
MCS1
MCS2
Selects the ratio between the input I2S sample
frequency and the input clock.
The STA335BWS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
" 32.768 MHz for 32 kHz
" 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
" 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs).
The relationship between the input clock and the input sample rate is determined by both
the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor
generating the internal clock and the IR bit determines the oversampling ratio used
internally
Table 10. Input sampling rates
Input sample rate
IR
fs (kHz)
101
32, 44.1, 48
00 576fs
88.2, 96
176.4, 192
01
NA
1X
NA
100
128fs
64fs
32fs
MCS[2:0)
011
256fs
128fs
64fs
010
384fs
192fs
96fs
001
512fs
256fs
128fs
000
768fs
384fs
192fs
25/68
Share Link: 