STA335BWS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA335BWS Datasheet PDF : 68 Pages
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Register description
STA335BWS
6.2.5 Channel input mapping
Bit R/W RST
Name
Description
6
R/W
0
7
R/W
1
C1IM
C2IM
0: Processing channel 1 receives Left I2S Input
1: Processing channel 1 receives Right I2S Input
0: Processing channel 2 receives Left I2S Input
1: Processing channel 2 receives Right I2S Input
Each channel received via I2S can be mapped to any internal processing channel via the
Channel Input Mapping registers. This allows for flexibility in processing. The default
settings of these registers map each I2S input channel to its corresponding processing
channel.
6.3
6.3.1
Configuration register C (addr 0x02)
D7
OCRB
1
D6
Reserved
D5
CSZ3
0
D4
CSZ2
1
D3
CSZ1
0
D2
CSZ0
1
D1
OM1
1
D0
OM0
1
DDX power output mode
Bit R/W RST
Name
Description
0
R/W
1
1
R/W
1
OM0
OM1
Selects configuration of DDX output.
The DDX power output mode selects how the DDX output timing is configured.
Different power devices use different output modes.
Table 14. Output modes
OM[1,0]
Output stage mode
00
Drop compensation
01
Discrete output stage - tapered compensation
10
Full power mode
11
Variable drop compensation (CSZx bits)
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