AT/TSC8x251G2D
AC Characteristics - Commercial & Industrial
AC Characteristics - External Bus Cycles
Definition of Symbols
Table 38. External Bus Cycles Timing Symbol Definitions
Signals
A
Address
H
D
Data In
L
L
ALE
V
Q
Data Out
X
R
RD#/PSEN#
Z
W
WR#
Conditions
High
Low
Valid
No Longer Valid
Floating
Timings
Test conditions: capacitive load on all pins = 50 pF.
Table 39 and Table 40 list the AC timing parameters for the TSC80251G2D derivatives
with no wait states. External wait states can be added by extending PSEN#/RD#/WR#
and or by extending ALE. In these tables, Note 2 marks parameters affected by one ALE
wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states.
Figure 8 to Figure 13 show the bus cycles with the timing parameters.
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4135F–8051–11/06