AT/TSC8x251G2D
Waveforms in Page Mode
Figure 10. External Bus Cycle: Data Write (Non-Page Mode)
ALE
TLHLL(1)
TWLWH(1)
TWHLH
WR#
TLHAX(1)
TAVLL(1) TLLAX
TQVWH
TWHQX
P0
A7:0
TAVWL1(1)
TAVWL2(1)
D7:0
Data Out
TWHAX
P2/A16/A17
A15:8/A16/A17
Note: 1. The value of this parameter depends on wait states. See Table 39 and Table 40.
Figure 11. External Bus Cycle: Code Fetch (Page Mode)
ALE
TLHLL(1)
TLLRL(1)
PSEN#(3)
P2
P0/A16/A17
TRLAZ
TLHAX(1)
TAVLL(1) TLLAX
TRLDV(1)
TRHDZ1
TRHDX
A15:8
TAVRL(1)
TAVDV1(1)
TAVDV2(1)
D7:0
Instruction In
D7:0
Instruction In
TAXDX
TAVDV3(1)
TRHAX
A7:0/A16/A17
Page Miss(2)
A7:0/A16/A17
Page Hit(2)
Note:
1. The value of this parameter depends on wait states. See Table 39 and Table 40.
2. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch)
requires one state (2·TOSC);
a page miss requires two states (4·TOSC).
3. During a sequence of page hits, PSEN# remains low until the end of the last page-hit
cycle.
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4135F–8051–11/06