Figure 12. External Bus Cycle: Data Read (Page Mode)
ALE
TLHLL(1)
TLLRL(1) TRLRH(1)
TRHLH2
RD#/PSEN#
TRLAZ
TLHAX(1)
TAVLL(1)
TLLAX
TRLDV(1)
TRHDZ2
TRHDX
P2
A15:8
D7:0
TAVRL(1)
TAVDV1(1)
TAVDV2(1)
Data In
TRHAX
P0/A16/A17
A7:0/A16/A17
Note: 1. The value of this parameter depends on wait states. See Table 39 and Table 40.
Figure 13. External Bus Cycle: Data Write (Page Mode)
ALE
TLHLL(1)
TWLWH(1)
TWHLH
WR#
TLHAX(1)
TAVLL(1) TLLAX
TQVWH
TWHQX
P2
A15:8
TAVWL1(1)
TAVWL2(1)
D7:0
Data Out
TWHAX
P0/A16/A17
A7:0/A16/A17
Note: 1. The value of this parameter depends on wait states. See Table 39 and Table 40.
AC Characteristics - Real-Time Synchronous Wait State
Definition of Symbols
Table 41. Real-Time Synchronous Wait Timing Symbol Definitions
Signals
Conditions
C
WCLK
R
RD#/PSEN#
W
WR#
Y
WAIT#
L
Low
V
Valid
X
No Longer Valid
50 AT/TSC8x251G2D
4135F–8051–11/06