AT80251G2D-3CSUM(2006) View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT80251G2D-3CSUM
(Rev.:2006)
(Rev.:2006)
Atmel Corporation
AT80251G2D-3CSUM Datasheet PDF : 77 Pages
| |||
Table 39. Bus Cycles AC Timings; VDD = 4.5 to 5.5 V, TA = -40 to 85°C
12 MHz
16 MHz
24 MHz
Symbol Parameter
Min Max Min Max Min Max Unit
TOSC 1/FOSC
83
62
41
ns
TLHLL ALE Pulse Width
78
58
38
ns(2)
TAVLL Address Valid to ALE Low
78
58
37
ns(2)
TLLAX Address hold after ALE Low
19
11
3
TRLRH(1) RD#/PSEN# Pulse Width
162
121
78
TWLWH WR# Pulse Width
165
124
81
ns
ns(3)
ns(3)
TLLRL(1) ALE Low to RD#/PSEN# Low
22
14
6
ns
TLHAX ALE High to Address Hold
99
70
40
ns(2)
TRLDV(1) RD#/PSEN# Low to Valid Data
146
104
61
ns(3)
TRHDX(1) Data Hold After RD#/PSEN# High
0
0
0
ns
TRHAX(1)
Address Hold After RD#/PSEN#
High
0
0
0
ns
TRLAZ(1) RD#/PSEN# Low to Address Float
0
0
0
ns
TRHDZ1
Instruction Float After RD#/PSEN#
High
45
40
30
ns
TRHDZ2 Data Float After RD#/PSEN# High
215
165
115
ns
TRHLH1
RD#/PSEN# high to ALE High
(Instruction)
49
43
31
ns
TRHLH2
RD#/PSEN# high to ALE High
(Data)
215
169
115
ns
TWHLH WR# High to ALE High
215
169
115
ns
TAVDV1 Address (P0) Valid to Valid Data In
250
175
105 ns(2)(3)
TAVDV2 Address (P2) Valid to Valid Data In
306
223
140 ns(2)(3)
TAVDV3
Address (P0) Valid to Valid
Instruction In
150
109
68
ns(3)
TAXDX Data Hold after Address Hold
0
0
0
ns
TAVRL(1) Address Valid to RD# Low
100
70
40
ns(2)
TAVWL1 Address (P0) Valid to WR# Low
100
70
40
ns(2)
TAVWL2 Address (P2) Valid to WR# Low
158
115
74
ns(2)
TWHQX Data Hold after WR# High
90
69
32
TQVWH Data Valid to WR# High
133
102
72
ns
ns(3)
TWHAX WR# High to Address Hold
167
125
84
ns
Notes: 1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·TOSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N = 1..3).
46 AT/TSC8x251G2D
4135F–8051–11/06
Share Link: 