PIC16F636T-I/SL(2005) View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F636T-I/SL
(Rev.:2005)

8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC12F635/PIC16F636/639

CALL

Call Subroutine

Syntax:

[ label ] CALL k

Operands:

0 ≤ k ≤ 2047

Operation:

(PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Description:

Call subroutine. First, return address

(PC + 1) is pushed onto the stack.

The eleven-bit immediate address is

loaded into PC bits <10:0>. The

upper bits of the PC are loaded from

PCLATH. CALL is a two-cycle

instruction.

CLRF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Clear f

[label] CLRF f

0 ≤ f ≤ 127

00h → (f)

1→Z

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

CLRW

Syntax:

Operands:

Operation:

Status Affected:

Description:

Clear W

[ label ] CLRW

None

00h → (W)

1→Z

Z

W register is cleared. Zero bit (Z)

is set.

CLRWDT

Syntax:

Operands:

Operation:

Status Affected:

Description:

Clear Watchdog Timer

[ label ] CLRWDT

None

00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

TO, PD

CLRWDT instruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT. Status bits,

TO and PD, are set.

COMF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Complement f

[ label ] COMF f,d

0 ≤ f ≤ 127

d ∈ [0,1]

(f) → (destination)

Z

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

register ‘f’.

DECF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Decrement f

[ label ] DECF f,d

0 ≤ f ≤ 127

d ∈ [0,1]

(f) – 1 → (destination)

Z

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘0’, the result is

stored back in register ‘f’.

DS41232B-page 134

Preliminary

© 2005 Microchip Technology Inc.

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