ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

Device architecture

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

Figure 29. Memory addressing scheme (example)

4M bytes

3FFFFFh

DPR3

DPR2

DPR1

DPR0

16K

294000h

240000h

23FFFFh

16K

20C000h

16K

200000h

1FFFFFh

DMASR

ISR

CSR

040000h

03FFFFh

64K

030000h

020000h

64K

010000h

16K

00C000h

64K

000000h

6.8

6.8.1

MMU usage

Normal program execution

Program memory is organized as a set of 64-Kbyte segments. The program can span as

many segments as needed, but a procedure cannot stretch across segment boundaries.

jps, calls and rets instructions, which automatically modify the CSR, must be used to

jump across segment boundaries. Writing to the CSR is forbidden during normal program

execution because it is not synchronized with the opcode fetch. This could result in fetching

the first byte of an instruction from one memory segment and the second byte from another.

Writing to the CSR is allowed when it is not being used, i.e during an interrupt service

routine if ENCSR is reset.

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Doc ID 8848 Rev 7

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