ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

Device architecture

Note:

6.8.2

A routine must always be called in the same way, i.e. either always with call or always with

calls, depending on whether the routine ends with ret or rets. This means that if the

routine is written without prior knowledge of the location of other routines which call it, and

all the program code does not fit into a single 64-Kbyte segment, then calls/rets should

be used.

In typical microcontroller applications, less than 64 Kbytes of RAM are used, so the four

Data space pages are normally sufficient, and no change of DPR[3:0] is needed during

Program execution. It may be useful however to map part of the ROM into the data space if

it contains strings, tables, bit maps, etc.

If there is to be frequent use of paging, the user can set bit 5 (DPRREM) in register R246

(EMR2) of Page 21. This swaps the location of registers DPR[3:0] with that of the data

registers of Ports 0-3. In this way, DPR registers can be accessed without the need to

save/set/restore the Page Pointer Register. Port registers are therefore moved to page 21.

Applications that require a lot of paging typically use more than 64 Kbytes of external

memory, and as ports 0, 1 and 9 are required to address it, their data registers are unused.

Interrupts

The ISR register has been created so that the interrupt routines may be found by means of

the same vector table even after a segment jump/call.

When an interrupt occurs, the CPU behaves in one of 2 ways, depending on the value of the

ENCSR bit in the EMR2 register (R246 on Page 21).

If this bit is reset (default condition), the CPU works in original ST9 compatibility mode. For

the duration of the interrupt service routine, the ISR is used instead of the CSR, and the

interrupt stack frame is kept exactly as in the original ST9 (only the PC and flags are

pushed). This avoids the need to save the CSR on the stack in the case of an interrupt,

ensuring a fast interrupt response time. The drawback is that it is not possible for an

interrupt service routine to perform segment calls/jps: these instructions would update

the CSR, which, in this case, is not used (ISR is used instead). The code size of all interrupt

service routines is thus limited to 64 Kbytes.

If, instead, bit 6 of the EMR2 register is set, the ISR is used only to point to the interrupt

vector table and to initialize the CSR at the beginning of the interrupt service routine: the old

CSR is pushed onto the stack together with the PC and the flags, and then the CSR is

loaded with the ISR. In this case, an iret will also restore the CSR from the stack. This

approach lets interrupt service routines access the whole 4-Mbyte address space. The

drawback is that the interrupt response time is slightly increased, because of the need to

also save the CSR on the stack. Compatibility with the original ST9 is also lost in this case,

because the interrupt stack frame is different; this difference, however, would not be

noticeable for a vast majority of programs.

Data memory mapping is independent of the value of bit 6 of the EMR2 register, and

remains the same as for normal code execution: the stack is the same as that used by the

main program, as in the ST9. If the interrupt service routine needs to access additional Data

memory, it must save one (or more) of the DPRs, load it with the needed memory page and

restore it before completion.

Doc ID 8848 Rev 7

73/523

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