LFSC3GA80E-7FN256I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA80E-7FN256I Datasheet PDF : 237 Pages
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Lattice Semiconductor
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
LatticeSC/M Internal Timing Parameters1 (Continued)
Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5%
-7
-6
-5
Parameter
Symbol
Description
Min. Max. Min. Max. Min. Max. Units
EBR Timing
tCO_EBR
CK_Q_DEL
Clock (Read) to output from Address
or Data
—
1.900
—
2.116
—
2.335
ns
tCOO_EBR
CK_Q_DEL
Clock (Write) to output from EBR
output Register
0.390 — 0.444 — 0.498 — ns
tSUDATA_EBR D_CK_SET
Setup Data to EBR Memory (Write
clk)
-0.173 — -0.192 — -0.210 —
ns
tHDATA_EBR D_CK_HLD
Hold Data to EBR Memory (Write clk) 0.276 — 0.305 — 0.335 —
ns
tSUADDR_EBR A_CK_SET
Setup Address to EBR Memory
(Write clk)
-0.165 — -0.182 — -0.200 — ns
tHADDR_EBR A_CK_HLD
Hold Address to EBR Memory (Write
clk)
0.269
—
0.298
—
0.327
—
ns
tSUWREN_EBR CE_CK_SET
Setup Write/Read Enable to EBR
Memory (Write/Read clk)
0.225 — 0.226 — 0.226 —
ns
tHWREN_EBR CE_CK_HLD
Hold Write/Read Enable to EBR
Memory (write/read clk)
0.073 — 0.095 — 0.116 — ns
tSUCE_EBR
CS_CK_SET
Clock Enable Setup Time to EBR
Output Register (Read clk)
0.261 — 0.269 — 0.276 —
ns
tHCE_EBR
CS_CK_HLD
Clock Enable Hold Time to EBR Out-
put Register (Read clk)
0.023
—
0.039
—
0.055
—
ns
tRSTO_EBR
RESET_Q_DEL
Reset To Output Delay Time from
EBR Output Register (asynchronous)
—
0.589
—
0.673
—
0.757
ns
Cycle Boosting Timing
tDEL1
DEL1
Cycle boosting delay 1 applies to
PIO, PFU, EBR
— 0.480 — 0.524 — 0.570 ns
tDEL2
DEL2
Cycle boosting delay 2 applies to
PIO, PFU, EBR
— 0.922 — 1.005 — 1.090 ns
tDEL3
DEL3
Cycle boosting delay 3 applies to
PIO, PFU, EBR
— 1.366 — 1.488 — 1.612 ns
1. Complete timing parameters for a user design will be incorporated when running ispLEVER. This is a sampling of the key timing parameters.
3-18
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