LFSC3GA80E-7FN256I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LFSC3GA80E-7FN256I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Input Delay Block/AIL Timing

Parameter

Description

Min.

tFDEL

Fine delay time

35

tCDEL

Coarse delay time

1120

jtAIL

AIL jitter tolerance

1- ((N1 * tFDEL) / (Clock Period))

1. N = number of fine delays used in a particular AIL setting

Typ.

45

1440

Max.

80

2560

Units

ps

ps

UI

GSR Timing

-7

-6

-5

Parameter

Description

VCC Min. Max. Min. Max. Min. Max.

tSYNC_GSR_MAX

Maximum operating frequency for

synchronous GSR

1.14V

0.95V

—

—

438

378

—

—

417

355

—

—

398

337

tASYNC_GSR_MPW

Minimum pulse width of

asynchronous input

—

—

—

—

—

3.3

—

Note: Synchronous GSR goes out of reset in two cycles from the clock edge where the setup time of the FF was met.

Units

MHz

MHz

ns

Internal System Bus Timing

-7

-6

-5

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

tHCLK

Maximum operating frequency for internal

system bus HCLK.

—

200

—

200

—

200 MHz

Note: There is no minimum frequency. If HCLK is sourced from the embedded oscillator, the minimum frequency limitation of the oscillator/

divider is about 0.3 MHz. Refer to the osciallator data for missing configuration modes.

3-19

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