LFSC3GA80E-7FN256I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LFSC3GA80E-7FN256I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

sysCLOCK PLL Timing

Over Recommended Operating Conditions

Parameter

Description

Conditions

Min. Typ

fIN

fOUT

Input Clock Frequency (CLKI, CLKFB)

Output Clock Frequency (CLKOP,

CLKOS)

2

—

1.5625 —

fVCO

PLL VCO Frequency

fPFD

Phase Detector Input Frequency

AC Characteristics

100

—

2

—

tDT

Output Clock Duty Cycle

Default duty cycle selected

(at 50% levels)

45

—

tOPJIT1

tCPJIT1

tSKEW

Output Clock Period Jitter

Output Clock Cycle-to-Cycle Jitter

Output Clock-to-Clock Skew (Between

Two Outputs with the Same Phase Set-

ting)

2 MHz ≤ fPFD ≤ 10 MHz

fPFD > 10 MHz

—

—

—

—

—

—

—

—

tLOCK

tIPJIT

tHI

tLO

tRSWA

tRSWD

tDEL

tRANGE

fSS

% Spread

PLL Lock-in Time

Input Clock Period Jitter

Input Clock High Time

Input Clock Low Time

Analog Reset Signal Pulse Width

Digital Reset Signal Pulse Width

Timeshift Delay Step Size

Timeshift Delay Range

Spread Spectrum Modulation Frequency

Percentage Downspread for SS Mode

At 80% level

At 20% level

—

—

—

—

350

—

350

—

100

—

3

—

40

80

— +/- 560

30

—

0.5

—

VCO Clock Phase Adjustment Accuracy

-5

—

1. Values are measured with FPGA logic active, no additional I/Os toggling and REFCLK total jitter = 30 ps

Max.

1000

1000

1000

700

55

200

100

100

20

1

±250

—

—

—

—

120

—

500

1.5

5

Units

MHz

MHz

MHz

MHz

%

ps

ps

ps

ps

ms

ps

ps

ps

ns

ns

ps

ps

KHz

%

°

3-25

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