LFSC3GA80E-7FN256I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LFSC3GA80E-7FN256I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Timing Diagrams

PFU Timing Diagrams

Figure 3-4. Slice Single/Dual Port Write Cycle Timing

CK

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

WRE

AD

AD

DI

D

DO Old Data

D

Notes:

• Rising Edge for latching WREN, WAD and DATAIN.

• WREN must continue past falling edge clock.

• Data output occurs on negative edge.

Figure 3-5. Slice Single/Dual Port Read Cycle Timing

CK

WRE

AD

AD

DO

Old Data

D

3-20

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