LFSC3GA80E-7FN256I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LFSC3GA80E-7FN256I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

sysCLOCK DLL Timing

Over Recommended Operating Conditions

Parameter

Description

Conditions

Min.

fIN

Input Clock Frequency (CLKI, CLKFB)

100

fOUTOP

Output Clock Frequency (CLKOP)

100

fOUTOS

Output Clock Frequency (CLKOS)

25

AC Characteristics

tDUTY

Output Clock Duty Cycle

Output Clock Duty Cycle (at 50%

levels, 50% duty cycle input clock,

duty cycle correction turned off,

38

time reference delay mode)

tDUTYRD

Output Clock Duty Cycle

Output Clock Duty Cycle (at 50%

levels, arbitrary duty cycle input

clock, duty cycle correction turned

45

on, time reference delay mode)

tDUTYCIR Output Clock Duty Cycle

Output Clock Duty Cycle (at 50%

levels, arbitrary duty cycle input

clock, duty cycle correction turned

40

on, clock injection removal mode)

tOPJIT1

Output Clock Period Jitter

—

tCPJIT1

Output Clock Cycle-to-Cycle Jitter

—

Output Clock to Clock Skew (Between

tSKEW

Two Outputs with the Same Phase

—

Setting)

tLOCK

tIDUTY

tIPJIT

tHI

tLO

tRSWD

tFDEL

tDLL

DLL Lock-in Time

8

Input Clock Duty Cycle

Applies to all operating conditions 35

Input Clock Period Jitter

—

Input Clock High Time

At 80% level

500

Input Clock Low Time

At 20% level

500

Reset Signal Pulse Width

3

Timeshift Delay Step Size

35

Delay Through the DLL when No Delay

Taps are Chosen but Not in Bypass

—

Mode.

1. Values are measured with FPGA logic active, no additional I/Os toggling and REFCLK total jitter = 30 ps.

Typ.

—

—

—

Max.

700

700

700

Units

MHz

MHz

MHz

—

62

%

—

55

%

—

60

%

—

200

ps

—

200

ps

—

100

ps

— 18500 cycles

—

65

%

— +/- 250 ps

—

—

ps

—

—

ps

—

—

ns

45

80

ps

760

—

ps

3-26

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