STM8S007C8T6TR(2015) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM8S007C8T6TR
(Rev.:2015)
(Rev.:2015)
STMicroelectronics
STM8S007C8T6TR Datasheet PDF : 92 Pages
| |||
Electrical characteristics
External
reset
circuit
(optional)
STM8S007C8
Figure 32. Recommended reset pin protection
VDD
STM8
0.1µF
NRST
RPU
Filter
Internal reset
9.3.8
SPI serial peripheral interface
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage
conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Symbol
Table 40. SPI characteristics
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
Slave mode
0
10
MHz
0
6
tr(SCK)
tf(SCK)
tsu(NSS)(1)
th(NSS)(1)
tw(SCKH)(1)
tw(SCKL)(1)
SPI clock rise and fall time
NSS setup time
NSS hold time
SCK high and low time
Capacitive load: C = 30 pF
Slave mode
Slave mode
Master mode
-
25
4 x tMASTER
-
70
-
tSCK/2 - 15 tSCK/2 + 15
tsu(MI) (1)
tsu(SI)(1)
Data input setup time
Master mode
Slave mode
5
-
5
-
th(MI) (1)
th(SI)(1)
Data input hold time
Master mode
Slave mode
7
-
ns
10
-
ta(SO)(1)(2)
tdis(SO)(1)(3)
tv(SO) (1)
tv(MO)(1)
th(SO)(1)
th(MO)(1)
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Slave mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
3 x tMASTER
25
-
-
75
-
30
31
-
12
-
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
72/92
DocID022171 Rev 5
Share Link: 