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STM8S105K6U3C View Datasheet(PDF) - STMicroelectronics

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Description
Manufacturer
STM8S105K6U3C Datasheet PDF : 127 Pages
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Electrical characteristics
STM8S105xx
Figure 42: SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
MISO
OUT P UT
MOSI
I NPUT
ta(SO)
tsu(SI)
tc(SCK)
tv(SO)
MS B O UT
th(SI)
M SB IN
th(SO)
BI T6 OUT
B I T1 IN
th(NSS)
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
LSB IN
ai14135
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 43: SPI timing diagram - master mode(1)
High
NSS input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
tc(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO
INP UT
tsu(MI)
MOSI
OUTU T
tw(SCKH)
tw(SCKL)
MS BIN
th(MI)
M SB OUT
tv(MO)
BI T6 IN
B I T1 OUT
th(MO)
tr(SCK)
tf(SCK)
LSB IN
LSB OUT
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
ai14136
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DocID14771 Rev 9

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